1. Field of the Invention
The present invention relates to a signal processing device and, more particularly, to a device for processing a signal at a level different from the levels of input and output signals. The invention also relates to a level converter circuit for converting the level of an input signal prior to the processing and for converting and outputting the level of the signal obtained by the processing.
2. Description of the Background Art
In general, an ECL level and a TTL level are often mixed when in use for an LSI in a user network interface (UNI) provided between ATM switches and an optical communication network in the Broadband Aspects of ISDN. Frequencies of signals to be processed are 19 MHz, 78 MHz, 156 MHz, and as high as 622 MHz.
When such signals are processed, it is necessary to employ a processing circuit formed by CMOS transistors for reduction in power consumption. With the current state of the art, however, it is difficult to process a signal having a frequency exceeding 200 MHz only by means of a processing circuit formed by CMOS transistors.
Accordingly, it has been proposed to apply a signal, if inputted, having a high frequency exceeding 200 MHz to a circuit at the ECL level, to produce an intermediate signal having a low frequency by serial-to-parallel conversion, and to perform predetermined signal processing on the intermediate signal by a processing circuit formed by CMOS transistors.
The potential of the logic at the ECL level is lower than that of the GND level, and the logic at the TTL level is higher than that of the GND level. Thus a level converter circuit for converting logic levels is required to process any signal at a CMOS level.
FIG. 12 is a block diagram of a signal processing device 101 for processing an input signal S.sub.in1 having a relatively low frequency, for example 19 MHz, and an input signal S.sub.in2 having a relatively high frequency, for example 622 MHz.
A signal processing circuit 101f performs signal processing at the CMOS level. The input signal S.sub.in1 having the low frequency is permitted to be processed in the signal processing circuit 101f without serial-to-parallel conversion. Thus, the input signal S.sub.in1 is applied to the signal processing circuit 101f only through a level converter circuit 101a for conversion from the TTL level to the CMOS level. After predetermined signal processing, the signal is outputted to the outside as an output signal S.sub.out1 through a level converter circuit 101b for conversion from the CMOS level to the TTL level.
The input signal S.sub.in2 having the high frequency is required to be received at the ECL level. Thus, an ECL input buffer 101c receives the input signal S.sub.in2. Then, a serial-to-parallel converter circuit 101d serial-to-parallel converts the input signal S.sub.in2 at the ECL level to provide a signal having a frequency processable by the signal processing circuit 101f. Further, a level converter circuit 101e for conversion from the ECL level to the CMOS level is provided for conversion into a signal at a level processable by the signal processing circuit 101f.
The signal processed by the signal processing circuit 101f is level converted by a level converter circuit 101g for conversion from the CMOS level to the ECL level, and is then parallel-to-serial converted at the ECL level by a parallel-to-serial converter circuit 101.sub.h into the original frequency. Then an output signal S.sub.out2 is provided through an ECL output buffer 101i.
FIG. 13 is a block diagram of another signal processing device 102 for processing the input signals S.sub.in1 and S.sub.in2. Signal processing is performed at a pseudo-CMOS level in the signal processing device 102. The pseudo-CMOS level (PCMOS level) represents a logic level at which logic identification is carried out at a potential lower than the GND level with the same potential difference as the CMOS level.
A level converter circuit 102a converts the input signal S.sub.in1 at the TTL level to the PCMOS level and applies the converted signal to a signal processing circuit 102f, which in turn performs predetermined signal processing on the signal. Then a level converter circuit 102b converts the processed signal to the TTL level to provide the output signal S.sub.out1.
An ECL input buffer 102c receives the input signal S.sub.in2. Then a serial-to-parallel converter circuit 102d serial-to-parallel converts the input signal S.sub.in2 at the ECL level. The ECL input buffer 102c and the serial-to-parallel converter circuit 102d may be of the same construction as the ECL input buffer 101c and the serial-to-parallel converter circuit 101d of the signal processing device 101 of FIG. 12, respectively.
A level converter circuit 102e for conversion from the ECL level to the PCMOS level is provided for conversion into a signal at a level processable by the signal processing circuit 102f. The signal processed by the signal processing circuit 102f is level converted by a level converter circuit 102g for conversion from the PCMOS level to the ECL level and is then parallel-to-serial converted at the ECL level by a parallel-to-serial converter circuit 102h into the original frequency. The output signal S.sub.out2 is provide through an ECL output buffer 102i.
The constructions of the signal processing devices 101 and 102 are disclosed in Proceeding of the 1994 IEICE (Institute of Electronics, Information and Communication Engineers of Japan) Spring Conference (C-625, Fujiwara, et al.).
The signal processing devices 101 and 102, however, present the problem of a large amount of consumed power during level conversion.
In the signal processing device 101, the serial-to-parallel converter circuit 101d provides a parallel signal. Thus, the level converter circuit 101e is required to level convert a plurality of signals, and is also required to perform the conversion from the ECL level which has a small logic level width (potential difference) and which is a negative-potential logic level to the CMOS level which has a large logic level width and which is a positive-potential logic level, resulting in a large amount of power consumed in the level converter circuit 101e.
In the signal processing device 102, the ECL level and the PCMOS level have different widths of logic levels to be converted similarly to the signal processing device 101 but both are negative potentials. Therefore, the amount of power consumed in the level converter circuit 102e is smaller than that in the level converter circuit 101e.
The signal processing device 102 is, however, required to perform the conversion from the TTL level which has a large logic level width and which is a positive-potential logic level to the PCMOS level which has a large logic level width and which is a negative-potential logic level. In the signal processing device 101, on the other hand, the level converter circuit 101a for conversion from the TTL level to the CMOS level is formed by a CMOS circuit and, accordingly, consumes little power.
Therefore, the amount of power consumed in the level converter circuit 102a is greater than that in the level converter circuit 101a. Since a number of ports are generally required to receive the input signal S.sub.in1 for use in the ISDN, the signal processing device 102 consumes a greater amount of power than the signal processing device 101 does.